Getting Started with IonQ Aria: Trapped Ion Quantum Computing

Trapped ion quantum computers operate on fundamentally different physics than superconducting processors. Where superconducting qubits are fabricated circuits cooled to millikelvin temperatures, trapped ion qubits are individual atomic ions levitated by electromagnetic fields in a vacuum chamber at room temperature. This architectural difference has sweeping consequences for error rates, connectivity, gate sets, and the kinds of algorithms that run well on each platform.

IonQ Aria is IonQ’s second-generation trapped ion system, offering 25 qubits with all-to-all connectivity and some of the lowest published two-qubit gate error rates in the industry. It is accessible through IonQ Quantum Cloud and Microsoft Azure Quantum (target ionq.qpu.aria-1). On Amazon Braket, IonQ’s currently listed devices are the newer 36-qubit Forte-1 and Forte-Enterprise-1, which share the same trapped ion architecture, so everything in this tutorial about ion physics, connectivity, and native gates carries over.

How Trapped Ion Qubits Work

Each qubit is a single ytterbium-171 (Yb+) ion, trapped in a linear Paul trap using oscillating electric fields. The qubit states are two hyperfine energy levels of the ion’s outer electron, separated by a microwave frequency of about 12.6 GHz. These energy levels are:

• |0> = the lower hyperfine ground state
• |1> = the upper hyperfine ground state

Transitions between these states are driven by laser pulses or microwave pulses, implementing single-qubit gates. The ions in the trap share collective vibrational modes (phonon modes), and entangling gates work by coupling ion pairs through these shared vibrations.

Key properties that flow from this architecture:

Long coherence times. Hyperfine qubit states are first-order insensitive to magnetic field fluctuations. Coherence times on IonQ systems are measured in seconds, compared to microseconds on superconducting platforms. This gives trapped ion circuits more time to run before decoherence becomes dominant.

All-to-all connectivity. Every ion in the trap interacts with every other ion through the shared phonon bus. There is no coupling map, no need for SWAP routing, and no nearest-neighbor constraint. An algorithm requiring a CNOT between any pair of qubits can implement it directly. On a 25-qubit system, this eliminates the routing overhead that increases circuit depth by 3-10x on superconducting hardware for many algorithms.

Lower gate throughput. Laser-driven two-qubit gates on trapped ions take longer than superconducting gates: typically 100-500 microseconds vs 100-500 nanoseconds. This makes trapped ion systems slower in raw gate rate, which matters for algorithms requiring millions of sequential gates.

The IonQ Aria Native Gate Set

IonQ Aria supports three native gates. All other gates are transpiled into combinations of these three:

GPi(phi): a single-qubit gate implementing a pi rotation about an axis in the equatorial plane of the Bloch sphere, parameterized by the azimuthal angle phi:

GPi(phi) = [[0,          exp(-i phi)],
            [exp(i phi),  0         ]]

GPi2(phi): a single-qubit gate implementing a pi/2 rotation about the same class of axes:

GPi2(phi) = (1/sqrt(2)) * [[1,          -i*exp(-i phi)],
                            [-i*exp(i phi), 1           ]]

MS(phi0, phi1): the Molmer-Sorensen gate, a native two-qubit entangling gate between any pair of ions. Named after the physicists who introduced it (Molmer and Sorensen), this gate creates maximal entanglement in a single operation:

MS(phi0, phi1) = (1/sqrt(2)) * [[1,   0,                    0,                    -i*exp(-i*(phi0+phi1)*2)],
                                  [0,   1,                    -i*exp(-i*(phi0-phi1)*2), 0                   ],
                                  [0,   -i*exp(i*(phi0-phi1)*2), 1,                    0                   ],
                                  [-i*exp(i*(phi0+phi1)*2), 0, 0,                    1                   ]]

When phi0 = phi1 = 0, MS produces the same entanglement as a CNOT up to single-qubit rotations. The double-parameterized form allows finer control over the entanglement axis, which can reduce total gate count for some circuits.

Unlike CNOT, the MS gate is symmetric: it does not have a control and a target. Both qubits participate equally, which simplifies some circuit constructions.

Accessing IonQ Hardware via Amazon Braket

Aria itself is no longer listed on Amazon Braket; the IonQ devices available there are Forte-1 and Forte-Enterprise-1. The Braket workflow is identical regardless of which IonQ generation you target. You need an AWS account with Braket permissions, and you will be charged per task and per shot:

import boto3
from braket.aws import AwsDevice
from braket.circuits import Circuit
from braket.devices import Devices

# List available IonQ devices
session = boto3.Session(region_name='us-east-1')

# IonQ Forte-1 device ARN (current IonQ device on Braket)
forte_arn = "arn:aws:braket:us-east-1::device/qpu/ionq/Forte-1"

# Fetch device properties (no cost, just metadata)
qpu = AwsDevice(forte_arn)
print(f"Device name:    {qpu.name}")
print(f"Status:         {qpu.status}")
print(f"Number of qubits: {qpu.properties.paradigm.qubitCount}")
print(f"Connectivity:   {qpu.properties.paradigm.connectivity.fullyConnected}")
print(f"\nNative gate set:")
for gate in qpu.properties.paradigm.nativeGateSet:
    print(f"  {gate}")

To run on Aria specifically, use IonQ Quantum Cloud or Azure Quantum (target ionq.qpu.aria-1). Note that Forte-generation systems expose a ZZ entangling gate as the native two-qubit gate in place of Aria’s MS gate; check the device’s nativeGateSet property before writing native-gate circuits.

Circuit Construction with Native Gates

The simplest way to build circuits for IonQ Aria is to write them in Braket’s high-level gate set (CNOT, H, Rz, etc.) and let Braket transpile automatically. For performance-critical circuits, writing directly in native gates eliminates transpilation overhead:

from braket.circuits import Circuit

# --- High-level circuit (Braket transpiles to native gates) ---
def bell_pair_highlevel():
    """Create a Bell pair using standard gates."""
    circ = Circuit()
    circ.h(0)
    circ.cnot(0, 1)
    return circ

# --- Native gate circuit (no transpilation needed) ---
def bell_pair_native():
    """
    Create a Bell pair using IonQ native gates.
    H = GPi2(0) followed by GPi(0)
    CNOT = MS gate followed by single-qubit corrections
    """
    circ = Circuit()

    # Hadamard on qubit 0: H = GPi2(-pi/2) * GPi(0) approximately
    # IonQ's exact decomposition uses:
    circ.gpi2(0, 0)      # GPi2(phi=0) on qubit 0

    # MS gate between qubits 0 and 1 (entangling gate)
    circ.ms(0, 1, 0, 0)  # MS(phi0=0, phi1=0)

    # Single-qubit corrections to match CNOT exactly
    circ.gpi2(0, 0.5)    # phi in units of turns (0.5 = pi radians)
    circ.gpi2(1, 0)

    return circ

# Inspect circuits
print("High-level Bell pair circuit:")
print(bell_pair_highlevel())
print("\nNative gate Bell pair circuit:")
print(bell_pair_native())

GHZ State and Verification

A 3-qubit GHZ state demonstrates all-to-all connectivity: we entangle qubits 0, 1, and 2 with gates between non-adjacent qubits (which would require SWAP routing on a superconducting chain):

def ghz_3qubit():
    """
    3-qubit GHZ state: (|000> + |111>) / sqrt(2)
    All gates are between arbitrary qubit pairs -- no routing overhead.
    """
    circ = Circuit()
    circ.h(0)
    circ.cnot(0, 1)
    circ.cnot(0, 2)   # direct gate from 0 to 2, not possible without SWAP on a linear chain
    circ.probability()  # add result type for measurement probabilities
    return circ

ghz = ghz_3qubit()
print("GHZ state circuit:")
print(ghz)

Running on a local simulator first:

from braket.devices import LocalSimulator

sim = LocalSimulator()
task = sim.run(ghz_3qubit(), shots=1000)
result = task.result()
print("\nSimulated GHZ probabilities:")
for state, prob in sorted(result.result_types[0].value.items()):
    if prob > 0.01:
        print(f"  |{state}>: {prob:.4f}")
# Expected: |000> ~0.5, |111> ~0.5

To run on IonQ hardware through Braket: pricing is $0.30 per task plus a per-[shot](/glossary/shot) fee ($0.08 per shot on Forte as of mid-2026, so a 100-shot run costs $8.30). For Aria access through IonQ Quantum Cloud or Azure Quantum, check those platforms’ pricing pages, as they bill differently:

# Run on IonQ hardware via Braket (uncomment when ready)
# qpu_task = qpu.run(ghz_3qubit(), shots=100)
# qpu_result = qpu_task.result()
# print("\nQPU GHZ probabilities:")
# for state, prob in sorted(qpu_result.result_types[0].value.items()):
#     if prob > 0.01:
#         print(f"  |{state}>: {prob:.4f}")

Aria vs. Forte: IonQ’s Current Systems

IonQ publishes algorithmic qubit (#AQ) benchmarks, which measure how many qubits can be used reliably in a suite of algorithmic benchmark circuits. Higher #AQ indicates better effective performance. Per IonQ’s published specifications:

Metric	IonQ Aria	IonQ Forte
Physical qubits	25	36
Algorithmic qubits (#AQ)	25	36
Connectivity	All-to-all	All-to-all
1Q gate fidelity	99.95%	see ionq.com
2Q gate fidelity (native)	99.6%	see ionq.com
Coherence time (T1)	10-100 s	10-100 s
Gate time (2Q)	~600 us	check current specs

(IonQ’s first-generation Harmony system, an 11-qubit device, was retired in 2023. Fidelity figures above are IonQ’s published averages; current calibration data is on ionq.com and in each cloud provider’s device properties.)

Aria’s two-qubit gate fidelity of around 99.6% places it among the highest-fidelity quantum computers publicly accessible. Leading superconducting processors have been closing this gap: IBM Heron achieves median two-qubit fidelities above 99.5% on its best pairs, and Google’s more recent processors (Willow) have reported similar numbers. The advantage of trapped ion systems lies in all-to-all connectivity and long coherence times rather than raw two-qubit gate fidelity alone.

When to Choose IonQ Over Superconducting Platforms

Choose IonQ Aria when:

• Your circuit requires many-qubit entanglement with non-local connectivity. Algorithms like quantum simulation of all-to-all Ising models, QAOA on dense graphs, and quantum chemistry with many interacting orbitals benefit from zero routing overhead.
• Your circuit depth is moderate but gate count is low. Trapped ion gates are slow but very accurate. If your circuit fits within coherence time (seconds), you will see much lower accumulated error than on superconducting hardware with faster but noisier gates.
• You need high two-qubit gate fidelity for variational algorithms (VQE, QAOA) where accumulated error directly degrades the optimization landscape.
• You are running quantum error correction experiments that need long coherence relative to gate time.

Choose superconducting platforms when:

• Your algorithm has very long gate sequences (millions of gates). Gate rate matters, and superconducting processors execute gates 1000x faster.
• You need more qubits than IonQ offers (25 on Aria, 36 on Forte). IBM has 100+ qubit processors; IonQ is scaling more slowly due to the physical complexity of trapping large ion crystals.
• You are prototyping and need low-cost, fast iteration cycles. Simulator mode for superconducting platforms is often closer to hardware performance at the current NISQ scale.

The choice between trapped ion and superconducting is not permanent. Many research groups run algorithms on both to compare. Amazon Braket makes this comparison straightforward since both IonQ and Rigetti (superconducting) are accessible from the same SDK with the same circuit interface. You can often run identical circuits on both backends and compare raw fidelity directly.