Circuit Depth

Circuit depth is the number of time steps needed to execute a quantum circuit, counting gates that can run simultaneously as a single step. It is the critical path length through the circuit’s directed acyclic graph, where each node is a gate and edges represent qubit dependencies. A circuit with 1,000 gates might have a depth of only 50 if most gates can be parallelized across different qubits.

Formal definition

Given a quantum circuit on $n$ qubits, partition the gates into layers $L_1, L_2, \ldots, L_d$ such that:

1. Every gate appears in exactly one layer
2. Gates within the same layer act on disjoint sets of qubits
3. If gate $g_a$ must precede gate $g_b$ (they share a qubit and $g_a$ comes first), then $g_a$‘s layer index is smaller than $g_b$‘s

The circuit depth is the minimum number of layers $d$ achievable.

For example, a circuit applying Hadamard gates to all $n$ qubits has depth 1 regardless of $n$, because all the gates act on different qubits and can execute simultaneously. A chain of $n$ CNOT gates where each shares a qubit with the next has depth $n$.

Why depth matters

On real hardware, every time step introduces errors. Each qubit accumulates decoherence proportional to the total circuit execution time, which scales with depth (not total gate count). If a circuit has depth $d$ and each layer takes time $\tau$, the total execution time is approximately $d \cdot \tau$. This time must be small compared to the qubits’ coherence times $T_1$ and $T_2$, or the computation’s results become dominated by noise.

A rough rule of thumb: the maximum useful circuit depth is approximately $T_2 / \tau_{\text{gate}}$, where $\tau_{\text{gate}}$ is the duration of the slowest gate type (usually the two-qubit gate). For superconducting qubits with $T_2 \sim 100\,\mu\text{s}$ and two-qubit gate time $\sim 200\,\text{ns}$, this gives a maximum depth of roughly 500. For trapped ions with $T_2 \sim 1\,\text{s}$ and two-qubit gate time $\sim 200\,\mu\text{s}$, the maximum depth is roughly 5,000.

Depth optimization

Transpilation often focuses on reducing circuit depth. Common strategies include:

• Gate commutation: Reordering gates that commute to enable more parallelism
• Gate cancellation: Removing adjacent inverse gate pairs (e.g., two consecutive CNOTs on the same qubits)
• Qubit routing: Inserting SWAP gates to satisfy connectivity constraints while minimizing added depth
• Circuit synthesis: Re-synthesizing subcircuits to find lower-depth implementations

The depth-width tradeoff is also important: using more ancilla qubits (increasing circuit width) can sometimes reduce depth by enabling parallel computation of intermediate results.

Depth in complexity theory

The quantum circuit complexity class $\text{QNC}^k$ contains problems solvable by quantum circuits of polylogarithmic depth $O(\log^k n)$. The question of whether $\text{QNC}^1$ (logarithmic depth) can solve the same problems as polynomial-depth circuits connects to deep questions about parallelism in quantum computation.

Why it matters for learners

When evaluating whether a quantum algorithm can run on current hardware, circuit depth is usually the binding constraint, not total gate count. IBM’s quantum volume metric directly incorporates achievable circuit depth as a measure of processor capability. Understanding depth helps you estimate whether a given algorithm is feasible on today’s NISQ devices.

See also

• Quantum Circuit
• Transpilation
• Coherence Time
• Quantum Volume
• Noisy Intermediate-Scale Quantum