Intel Silicon Spin Qubit: Leveraging Semiconductor Fabrication for Quantum Computing

The Problem

Every competing qubit modality faces a manufacturing cliff. Superconducting qubits require specialized deposition processes and operate at millikelvin temperatures that are difficult to wire at scale. Trapped ion systems are precise but slow to manufacture. Silicon spin qubits offer a different bet: fabricate qubits using the same 300mm wafer processes that already produce billions of transistors per day, and exploit decades of CMOS engineering investment to scale toward the million-qubit systems that fault-tolerant quantum computing requires.

Intel’s Quantum Research group set out to prove that spin qubit devices with competitive fidelity could be produced on a standard semiconductor production line, not a specialized research fab.

Silicon Spin Qubits and the Tunnel Falls Chip

A silicon spin qubit encodes quantum information in the spin state (up or down) of a single electron confined in a quantum dot formed by electrostatic gates on a silicon-silicon germanium heterostructure. Gate voltages control the electron’s position, and microwave pulses drive spin rotations. The entire structure is fabricated using conventional lithography tools.

Intel’s Tunnel Falls chip integrates 12 spin qubits on a die produced on Intel’s 300mm process line. Key measured parameters include T2 coherence times around 100 microseconds and single-qubit gate fidelities exceeding 99%, competitive with leading superconducting implementations.

# Intel Quantum SDK: running a single-qubit gate sequence on Tunnel Falls
from intel_qs import QuantumSimulator, Circuit, Gate

# Simulate the Tunnel Falls native gate set
sim = QuantumSimulator(num_qubits=12)
circ = Circuit(num_qubits=12)

# Native gates: X-rotation (Rx) and virtual Z (phase shift)
circ.add_gate(Gate.Rx(qubit=0, angle=3.14159))   # X gate via microwave pulse
circ.add_gate(Gate.Rz(qubit=0, angle=1.5708))    # Virtual Z: software frame rotation
circ.add_gate(Gate.CZ(control=0, target=1))       # Two-qubit entangling gate

result = sim.run(circ, shots=10000)
print(result.counts)

Horse Ridge II: Cryogenic Control at Scale

The qubit count problem is inseparable from the control wiring problem. Each qubit classically requires its own microwave line running from room-temperature electronics into the dilution refrigerator, and cable heat load limits total wire count to a few hundred at best. Intel’s Horse Ridge II cryogenic control chip runs at 4 Kelvin (cold enough to sit inside the cryostat, hot enough to be powered without thermal overload) and multiplexes control signals for up to 128 qubits from a single chip. It handles frequency synthesis, pulse shaping, and qubit readout in situ, slashing the wire count by two orders of magnitude.

This is the architectural unlock that makes the million-qubit roadmap plausible: if Horse Ridge II can control 128 qubits per chip, a rack of cryogenic controllers can manage a full fault-tolerant processor without a cable-count catastrophe.

The Scalability Argument

The strategic advantage Intel is betting on is straightforward. Superconducting qubit fabs are specialized, low-volume, and expensive to scale. Intel’s 300mm fabs run 24 hours a day producing chips at extremely high volume with tight process controls and established yield management. Applying that infrastructure to spin qubit production means that once the process is locked in, qubit count can scale with wafer throughput rather than bespoke fabrication effort.

The current challenge is crosstalk: at high qubit density, the electrostatic gates that define neighboring qubits interact, shifting resonance frequencies and degrading fidelity. Intel’s process team is working through layout rules and shielding structures to suppress cross-capacitance, drawing directly on their transistor scaling playbook. The Condor roadmap targets 1 million+ spin qubits using these CMOS-compatible processes, with Horse Ridge successors providing the matching control infrastructure.