Samsung Quantum Computing for Semiconductor Process Optimization

The Problem

Manufacturing a 3nm logic chip requires precisely controlling hundreds of interdependent process parameters across lithography, etch, deposition, and anneal steps. For a single gate etch process, variables include plasma power, chamber pressure, gas flow ratios, electrode temperature, and bias voltage, each interacting with the others in ways that shift etch rate, profile angle, and selectivity. Finding the process window (the region of parameter space where yield stays above target across natural process variation) is a high-dimensional search problem that classical Design of Experiments handles with factorial or response surface designs requiring hundreds of expensive wafer runs.

Samsung Research and Quantinuum explored whether QAOA could find a larger, more centered process window with fewer evaluations than classical DoE, reducing the number of wafer runs needed to qualify a new process node.

QUBO Formulation for Process Window Definition

The team discretized each process parameter into bins and encoded the selection of a bin for each parameter as a binary variable. The objective function rewarded process windows where the simulated yield stayed above 95% across a Monte Carlo sample of parameter perturbations, with penalty terms preventing physically infeasible combinations (for example, plasma power settings that would exceed chamber thermal limits or gas flows that would starve the reaction).

The interaction terms in the QUBO captured physical coupling between variables. Plasma power and pressure interact strongly (higher power at lower pressure increases ion energy and changes etch selectivity), so their coupling coefficient was derived from a pre-trained surrogate model fit to historical process data.

from pytket.extensions.quantinuum import QuantinuumBackend
from pytket.circuit import Circuit
import numpy as np

# Build QAOA circuit for process window QUBO
# n_params process parameters, each discretized to k bins
# total qubits = n_params * k_bins (one-hot encoding)

n_params = 6   # plasma power, pressure, O2 flow, CF4 flow, temp, bias
k_bins   = 8   # 8 discretization levels per parameter
n_qubits = n_params * k_bins  # 48 qubits

def build_qaoa_circuit(gamma, beta, qubo_matrix, p_layers=3):
    circ = Circuit(n_qubits)
    # Initial superposition
    for q in range(n_qubits):
        circ.H(q)
    for layer in range(p_layers):
        # Problem unitary: encode QUBO interactions as ZZ rotations
        for i in range(n_qubits):
            for j in range(i + 1, n_qubits):
                if abs(qubo_matrix[i, j]) > 1e-6:
                    angle = gamma[layer] * qubo_matrix[i, j]
                    circ.ZZPhase(angle / np.pi, i, j)
        # Mixer unitary: X rotations
        for q in range(n_qubits):
            circ.Rx(2 * beta[layer] / np.pi, q)
    circ.measure_all()
    return circ

backend = QuantinuumBackend(device_name="H2-1")
backend.login()

gamma_init = np.random.uniform(0, np.pi, 3)
beta_init  = np.random.uniform(0, np.pi, 3)
circ = build_qaoa_circuit(gamma_init, beta_init, qubo_matrix)
compiled = backend.get_compiled_circuit(circ, optimisation_level=2)
handle = backend.process_circuit(compiled, n_shots=2000)
result = backend.get_result(handle)

Comparison to Classical Design of Experiments

Classical DoE approaches for process window definition use either a full factorial design (exhaustive but exponentially expensive) or a central composite design (efficient but assumes smooth quadratic response). For a 6-parameter gate etch process, a standard central composite design requires around 80 wafer runs to fit a response surface model and locate the process window center.

QAOA on the Quantinuum H2 processor found candidate process windows by sampling the QUBO energy landscape across 2,000 shots per optimization step, with classical variational parameter updates between steps. The quantum sampler’s ability to explore non-local regions of the parameter space in a single shot (rather than evaluating one parameter combination at a time) allowed it to identify a process window 12% larger than the classical DoE baseline in simulation. The larger window means more margin against wafer-to-wafer process drift, which directly translates to higher yield in production.

Validation Path and Next Steps

All results so far are simulation-validated using Samsung’s in-house process simulator, not actual wafer runs. The 12% process window improvement is relative to the simulator’s prediction of what classical DoE would find, which introduces model assumptions about how accurately the simulator captures real fab behavior.

Samsung’s fab process team is designing a validation experiment to run the QAOA-identified process window candidates on actual etch tools alongside the classical DoE baseline. If the simulation advantage holds in hardware, the methodology would be extended to lithography focus-exposure matrix optimization and deposition thickness uniformity tuning, both higher-dimensional problems where the quantum advantage could be proportionally larger. Quantinuum’s H2 processor was selected specifically for its high two-qubit gate fidelity (above 99.8%), which is critical for maintaining solution quality in the multi-layer QAOA circuits required for 48-qubit problems.