Quantum Error Budget

A quantum error budget treats circuit fidelity as a product of individual error contributions. Under the multiplicative error model, the total success probability of a circuit is approximately the product of the per-operation fidelities: if a 100-gate circuit has each gate at 99.9% fidelity, the overall fidelity is roughly (0.999)^100, or about 90%. This framing makes it possible to set concrete targets for each hardware component and immediately see how improving one layer of the stack propagates to overall circuit performance.

The major sources that appear in a practical error budget include T1 relaxation (energy decay) and T2 dephasing (phase randomization), gate calibration errors from imperfect pulse shaping or timing, leakage to non-computational states outside the qubit subspace, crosstalk between neighboring qubits during simultaneous gates, and readout assignment errors that misclassify the measured bit. Each source is characterized by a rate or probability per operation, and the budget sums these contributions to estimate the total noise floor. Readout errors often dominate on current superconducting and trapped-ion devices at the 1% level, while two-qubit gate errors sit between 0.1% and 1%.

Error budgets are central to resource estimation for fault-tolerant algorithms. Given a target logical error rate per logical gate (say 10^-10 for a useful chemistry calculation), and a physical error rate drawn from the budget, the surface code threshold and code distance determine how many physical qubits are needed per logical qubit. Running the budget in reverse (starting from an algorithm’s T-gate count and desired success probability) lets researchers calculate the total physical qubit count and runtime, quantifying the gap between today’s hardware and the requirement for practical quantum advantage.

Microsoft’s Azure Quantum Resource Estimator and IBM’s resource estimation tooling both expose explicit error budget parameters. The Azure estimator partitions the budget into three components: logical errors per algorithmic step, T-factory distillation errors, and rotation synthesis errors, each receiving a fraction of the total allowed failure probability (commonly set at 1%). Practitioners adjust the split to match their hardware’s dominant noise source, enabling design-space exploration across different qubit technologies and code families before any hardware is built.